1. Field of the Invention
The present invention relates to semiconductor devices and methods for making the semiconductor devices. In particular, it relates to increasing the speed of and decreasing the power consumption of a MIS-type transistor having a hetero junction structure in which two types of semiconductor layers having different lattice constants are laminated.
2. Description of the Related Art
Speeding up and refinement of a MIS-type transistor by using a single semiconductor such as silicon (Si) have been pursued according to the scaling law but are now about to reach their limits. As a breakthrough to this situation, development of a technology that changes the physical properties of the channel material, i.e., a MOS-transistor having a heterojunction structure in which a layer with a different lattice constant is introduced to apply a strain onto the laminated crystals to form a channel and to thereby increase the carrier mobility, is now actively studied (e.g., Non-patent document 1).
FIG. 1 is a schematic cross-sectional view of a strained MOS-transistor in which a silicon germanium (SiGe) layer having a lattice constant larger than that of a Si layer is provided in addition to the Si layer. In this strained SiGe MOS transistor, a semiconductor film 111 is formed by epitaxially growing a SiGe layer 102 on a Si substrate 101 and then forming thereon a Si layer 103 which serves as a cap film for forming a gate insulating film, and a gate electrode 105 is formed on the semiconductor film 111 with a gate insulating film 104 therebetween. A side wall insulating film 108 is formed on the side wall of the gate electrode 105 so as to also cover part of the surface of the semiconductor film 111. A dopant is introduced into the semiconductor film 111 in regions at the both sides of the gate electrode 105 so that an extension region 106 and a source/drain region 107 define a channel region and that the compressive strain is introduced to the channel region.
According to a p-type MOS transistor having such a structure, the SiGe layer 102 having a compressive strain forms a hole channel layer; thus, hole mobility can be remarkably enhanced and the driving current can be increased.
In an n-type MOS transistor, the Si layer 103 and the SiGe layer 102 function as electron channel layers with low electric field.    Non-patent document 1: Sophie Verdonckt-Vandebroek et al., “SiGe-Channel Heterojunction p-MOSFET's”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol, 41, p. 90 (1994)